Full-Chip Physical Design Verification Engineer

Job summary

Responsibilities

Compensation for all engineers at Tenstorrent ranges from $100k - $500k including base and variable compensation targets. Experience, skills, education, background and location all impact the actual offer made.

• Advanced physical verification methodologies and flow optimization for next-generation SoCs.
• Integration and verification strategies for full-chip signoff across advanced process technologies.
• Cross-functional collaboration across design, CAD, and foundry teams to ensure flawless tapeouts.
• Leadership and mentoring opportunities in building scalable PV methodologies and automation.

What they're looking for

• A seasoned engineer with a strong background in CPU/IP/SoC physical verification and tapeout closure.
• A hands-on problem solver who excels at debugging and driving signoff through complex verification flows.
• A collaborative team player who works effectively across RTL, PD, CAD, and foundry interfaces.
• A mentor and technical leader passionate about building efficient, manufacturable silicon.

Tech stack

• Python