Staff/Sr. Staff Design Verification

Job summary

Responsibilities

If you're passionate about tackling complex challenges, making an impact, and being an expert in your craft, join our team of brilliant scientists, engineers, and accomplished industry leaders.

• Define and enhance the DV methodologies required for integrated digital, analog, and photonic devices with a strong emphasis on emulation for design verification.
• Create and execute test plans to ensure high-quality tapeouts that meet functional and performance goals, while leveraging emulation where appropriate.
• Collaborate with architects, DV engineers, digital designers, and analog/photonics designers to define validation flows.
• Create reusable and scalable test bench components that enable efficient and effective verification.
• Close coverage and finish all DV signoff requirements, with a focus on leveraging mixed signal simulations to achieve high coverage metrics

What they're looking for

• Bachelor’s degree in Electrical Engineering, Computer Engineering, a related field, or equivalent experience
• Minimum of 8 years of design verification and SystemVerilog experience
• 2+ years of experience in Python
• Expertise in developing with the UVM library
• Experience with simulators such as Xcelium, ModelSim, Questa, or VCS

Tech stack

• Python