Sr. Staff Physical Design Timing Engineer (STA)

Job summary

Responsibilities

If you're passionate about tackling complex challenges, making an impact, and being an expert in your craft, join our team of brilliant scientists, engineers, and accomplished industry leaders.

• Drive the STA sign-off for our flagship Silicon photonics chips at various technology nodes.
• Analyze fab guidelines and work with the methodology team to incorporate sign off corners, margins, and derates into timing analysis flows and methodologies.
• Collaborate with the architecture, RTL, and DFT teams to analyze the timing complexities and develop consolidated timing modes and constraints for synthesis, along with PnR and…
• Analyze and understand the tradeoffs between power/performance and area goals to drive them into overall chip implementation flows.
• Run full-chip STA and accurately project the timing summary across scenarios.

What they're looking for

• Bachelor’s degree in Electrical Engineering or Computer engineering
• 12 years of Physical Design experience, with a minimum of 5 years hands-on experience in ASIC STA and timing constraints development, timing closure with Cadence or Synopsys tools
• Experience in driving timing closure by effectively managing on-chip variation derates, optimizing multi-mode multi-corner constraints, and implementing robust clock tree…
• Well versed with scripting languages like TCL and Python, PERL, or Shell
• Strong problem solving skills with attention to every technical aspect

Tech stack

• Python