RTL Design Engineer – Interconnect & Network Datapath

Job summary

Responsibilities

We are looking for a highly experienced, hands-on RTL engineer with deep packet-networking and interconnect expertise to own critical on- and off-chip communication components for our custom AI accelerator platform.

• Own the microarchitecture, RTL design, and delivery of major packet-based interconnect and networking components, including NoC fabrics, switches, routers, bridges, protocol…
• Design mechanisms for routing, arbitration, ordering, flow control, congestion management, quality of service, packet scheduling, buffering, and performance monitoring.
• Develop on-chip and off-chip interfaces, protocol bridges, and custom networking protocols or protocol extensions for scale-up and scale-out systems.
• Perform substantial direct microarchitecture, SystemVerilog coding, simulation, and debug work.
• Collaborate with architecture and performance teams to analyze traffic patterns, identify bottlenecks, and optimize latency, bandwidth, fairness, and utilization under realistic…

What they're looking for

• Extensive industry experience with recent, hands-on ownership of complex networking, packet-processing, or packet-switched interconnect RTL.
• Demonstrated networking expertise in one or more of the following: Ethernet switching, NIC/SmartNIC/DPU datapaths, network accelerators, RDMA/RoCE, InfiniBand, traffic…
• Deep expertise in Verilog/SystemVerilog and the development of clean, parameterized, production-quality RTL.
• A strong record of owning major RTL blocks or SoC subsystems from requirements and microarchitecture through tape-out and silicon bring-up.
• Experience designing queues, arbiters, schedulers, buffers, routing logic, virtual channels, credit-based flow control, congestion management, quality of service, ordering, or…