Principal RTL Design Engineer

Job summary

Responsibilities

SambaNova is looking for a Principal RTL Design Engineer to own the microarchitecture and RTL for our next-generation Reconfigurable Dataflow Unit (RDU), the silicon behind our AI acceleration systems.

• Own the microarchitecture and RTL for a major block or subsystem of the RDU, from specification through tape-out, including the specs you write for complex blocks in compute…
• Write, integrate, and debug synthesizable SystemVerilog RTL through the full chip implementation and production lifecycle
• Own PPA for your area, hitting aggressive frequency targets through datapath pipelining, retiming, and microarchitectural restructuring
• Drive timing closure and design quality for your area: synthesis, STA, critical-path iteration, lint, CDC, LEC, and SystemVerilog Assertions capturing design intent
• Partner with design verification to define verification intent and coverage for your block, and support debug of functional and gate-level failures

What they're looking for

• B.S. in Electrical Engineering, Computer Engineering, or Computer Science
• 7+ years of industry experience in ASIC RTL design
• Mastery of synthesizable SystemVerilog for high-speed, high-performance ASICs, including SVA to capture design intent
• High-frequency design experience, including datapath pipelining, retiming, critical-path restructuring, and other microarchitectural techniques for hitting aggressive frequency…
• Deep foundation in computer architecture and digital logic design, including arbitration, flow control, clock domain crossing, and memory structures

Tech stack

• Python