Lead RTL Design Engineer

Job summary

Responsibilities

As a lead front-end design engineer, you will be a key part of the world-class team designing and developing the next generations of the Cerebras Wafer Scale Engine (WSE).

• Drive all aspects of chip design, including Functional Specification, Micro-architecture, RTL development, Synthesis.
• Managing external ASIC vendor through product development cycle.
• Work closely with PD team members for design closure to meet PPA goals.
• Work closely with Design verification and DFT teams for achieving the best functional and test coverage.
• Work with software and system teams to understand opportunities to deliver optimal performance and feature set for the product.

What they're looking for

• Master’s degree in Computer Science, Electrical Engineering, or equivalent.
• Can work in a hybrid work environment.
• 8-15 years of experience in delivering complex, high performance high quality RTL designs.
• Experience with Front End Chip integration and third-party IP integration.
• Demonstrated experience in networking, high-performance computing, machine learning or related fields.

Tech stack

• Python