Design Verification Engineer

Job summary

Responsibilities

SambaNova Systems is looking for a talented and motivated Design Verification Engineer, DFT to help us build state of the art RDU chips for machine learning and artificial intelligence.

• Develop and execute comprehensive verification plans for complex chip-level control and initialization features
• Develop SystemVerilog/UVM based verification environments, test sequences, checkers, assertions, and functional coverage
• Verify complex sequencing, dependencies, state transitions, and recovery scenarios across multiple chip subsystems
• Develop directed and constrained-random tests to identify architectural and implementation corner cases
• Closely work with architects, RTL designers, firmware, and other verification teams to understand design intent and drive verification closure

What they're looking for

• B.S. in Computer Science, Computer Engineering, or related field
• 5+ years relevant industry experience
• Strong understanding of digital design, SoC architecture, and verification methodologies
• Strong proficiency in SystemVerilog and UVM is required
• Experience with constrained-random verification, functional coverage, and assertion-based verification

Tech stack

• Python