Design Verification Engineer

Job summary

Responsibilities

OpenAI is developing custom silicon to power the next generation of frontier AI models. We’re looking for experienced Design Verification (DV) Engineers to ensure functional correctness and robust design for our cutting-edge ML accelerators.

• Own the verification of one or more of: custom IP blocks, subsystems (compute, interconnect, memory, etc.), or full-chip SoC-level functionality.
• Define verification plans based on architecture and microarchitecture specs.
• Develop constrained-random, directed, and system-level testbenches using SystemVerilog/UVM or equivalent methodologies.
• Build and maintain stimulus generators, checkers, monitors, and scoreboards to ensure high coverage and correctness.
• Drive bug triage, root cause analysis, and work closely with design teams on resolution.

What they're looking for

• BS/MS in EE/CE/CS or equivalent with 3+ years of experience in hardware verification.
• Proven success verifying complex IP or SoC designs in industry-standard flows
• Proficient in SystemVerilog, UVM, and common simulation and debug tools (e.g., VCS, Questa, Verdi).
• Strong knowledge of computer architecture concepts, memory and cache systems, coherency, interconnects, and/or ML compute primitives.
• Familiarity with performance modeling, formal verification, or emulation is a plus.